1. Field of the Invention
The present invention relates to a Time-to-Digital Converter (TDC) and an operation method thereof. More particularly, the present invention relates to a TDC having a high resolution at a Radio Frequency (RF) input frequency by using a Phase-Interpolation (PI) technique and a Time Amplifier (TA), and an operation method thereof.
2. Description of the Related Art
A wireless communication transceiver and the like include a phase-locked loop to provide a Local Oscillator (LO) frequency. Conventionally, an analog phase-locked loop is used, which may cause a reduction in process scale. To solve these and other problems, the analog phase-locked loop may be digitally constructed. In this case, however, the analog phase-locked loop may be insensitive to process variations. To overcome the insensitivity of the analog phase-locked loop, a digital phase-locked loop is used. In the digital phase-locked loop, a Time-to-Digital Converter (TDC) is used to detect a phase difference between an output frequency of a digital oscillator and a reference frequency, and the performance of the digital phase looked loop depends on a resolution of the TDC. The TDC receives two input signals, and delays one of the input signals through a delay line step by step. The TDC compares a waveform of the input signal delayed step by step with a waveform of the other input signal in terms of the rising edge, and outputs the comparison results in a digital code. A phase difference between the two input signals may be identified based on the output digital code.
FIG. 1 schematically illustrates a TDC with a single delay line according to the related art.
Referring to FIG. 1, a TDC 100 includes two input signal lines, L inverters 106-1˜106-L for signal delay, and (L+1) comparators 108-0˜108-L, which are implemented with their associated flip-flops.
The TDC 100 receives two input signals: a Digital Controlled Oscillator (DCO) frequency FDCO 102 and a reference frequency FREF 104. The FDCO 102 is delayed by each of the L inverters 106-1˜106-L and then input to each of the (L+1) comparators 108-0˜108-L. Each of the (L+1) comparators 108-0˜108-L compares a rising edge of the FDCO delayed by each of the inverters 106-1˜106-L with a rising edge of the FREF 104, and outputs the comparison results in a digital code. A phase difference between the input signals may be identified based on the output digital code.
A resolution of the TDC 100 is determined by a delay time of the inverters 106-1˜106-L. Since a delay time of an inverter is determined by a size of a transistor constituting the inverter, a resolution of the TDC may be limited to a specific value in a specific process.
Therefore, a need exists for a TDC having a high resolution at a Radio Frequency (RF) input frequency by using a Phase-Interpolation (PI) technique and a Time Amplifier (TA), and an operation method thereof.